High-NA EUV and Graph Transformers: Engineering the Sub-2nm Future
The semiconductor industry is moving toward High-NA EUV lithography and 3D mask effects to continue the march toward 2nm and below. Simultaneously, new research into Graph Transformers is speeding up signal integrity analysis for complex IC interconnects by orders of magnitude.
As the semiconductor industry pushes toward the absolute limits of Moore’s Law, the tools used to design and manufacture chips are undergoing a radical transformation. Two significant breakthroughs are currently at the forefront: the adoption of High Numerical Aperture (High-NA) Extreme Ultraviolet (EUV) lithography and the application of AI to signal integrity analysis.
High-NA EUV is essential for printing the incredibly fine features required for 2nm process nodes. Research from Fraunhofer and ASML indicates that three-dimensional mask (M3D) effects, once considered a nuisance, can actually be leveraged to enhance imaging quality. By optimizing these 3D effects, manufacturers can achieve better contrast and resolution, reducing the need for costly "multi-patterning" steps that slow down production and lower yields.
On the design side, the complexity of modern integrated circuit (IC) interconnects has made traditional signal integrity analysis a massive computational burden. Researchers from IBM and the University at Buffalo have introduced "SI-GT," a Graph Transformer-based approach that analyzes chip interconnects significantly faster than traditional SPICE-based simulations. By treating the chip's internal wiring as a massive graph, the AI can predict signal degradation and interference with high accuracy, drastically shortening the design cycle for the next generation of AI accelerators and SDV processors.
Source: Semiconductor Engineering
