Beyond Silicon: Engineering Tellurium for Next-Gen Transistors
Researchers are uncovering new ways to engineer transistors using ultrathin Tellurium to manage noise and improve performance in next-generation chips.
As traditional silicon scaling reaches its physical limits, the semiconductor industry is looking toward novel materials to maintain the pace of Moore’s Law. Researchers at the Pohang University of Science and Technology (POSTECH) have published breakthrough findings on the use of ultrathin Tellurium transistors. By conducting bias- and temperature-dependent noise measurements, the team has successfully revealed the "contact-origin noise" that often plagues 2D semiconductors, hindering their performance at smaller scales.
Engineering the interface between these 2D materials and their metal contacts is crucial for developing high-efficiency, low-power transistors. This research provides a roadmap for mitigating carrier transport noise, potentially paving the way for Tellurium to become a viable candidate for post-silicon electronics. As AI workloads demand increasingly efficient silicon, these material science breakthroughs at the transistor level will be the foundation upon which future neural processing units are built.
